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cmos(ADM)


cmos -- display and set the configuration database

Syntax

cmos [ address [ value ] ]

Description

The cmos command displays and/or sets the values in the battery-powered CMOS configuration database.

The 64-byte CMOS database stores the hardware configuration of the PC. A manufacturer-specific key combination, such as <Ctrl><Alt><Esc>, is typically used to access the manufacturer's CMOS setup program. Refer to your PC hardware documentation for the key combination for your machine, which must be entered before the operating system boots.

The operating system cmos command can be used to read or write CMOS information while running under an SCO OpenServer(TM) system.

cmos with no arguments lists the contents of the CMOS database, one byte per line, in the format:

address value

where address is the hexadecimal byte address and value is the hexadecimal value at that address.

cmos address will return the hexadecimal value of the byte at address. address can be specified in decimal, hexadecimal (precede it with ``0x''), or octal (precede it with ``0'').

cmos address value will set the byte at address to value. address and value can be specified in decimal, hexadecimal, or octal, as explained above.


NOTE: The computer manufacturer's diagnostic disk should be run before setting the CMOS database.

CMOS address map

The first 14 bytes of CMOS RAM store information about the real-time clock:

Real-time clock byte map

Byte address
(in hex)
Description
0 Seconds
1 Second alarm
2 Minutes
3 Minute alarm
4 Hours
5 Hour alarm
6 Day of week
7 Date of month
8 Month
9 Year
a Status register A

Bit 7
update in progress (UIP) -- a 1 indicates the time cycle update is in progress. A 0 indicates the current date and time are available to read.

Bit 6 - Bit 4
22-stage divider (DV2 through DV0) -- these three divider-selection bits identify which time-base frequency is being used. The system initializes the stage divider to 010, which selects a 32.768-kHz time base.

Bit 3 - Bit 0
rate selection bits (RS3 through RS0) -- these bits allow the selection of a divider output frequency. The system initializes the rate selection bits to 0110, which selects a 1.024-kHz square wave output frequency and a 976.562-microsecond periodic interrupt rate.
b Status register B

Bit 7
set -- a 0 updates the cycle normally by advancing the counts at one per second. A 1 aborts any update cycle in progress and the program can initialize the 14 time-bytes without any further updates occurring until a 0 is written to this bit.

Bit 6
periodic interrupt enable (PIE) -- this bit is a read/write bit that allows an interrupt to occur at a rate specified by the rate and divider bits in register A. A 1 enables an interrupt and a 0 disables it. The system initializes this bit to 0.

Bit 5
alarm interrupt enable (AIE) -- a 1 enables the alarm interrupt and a 0 disables it. The system initializes this bit to 0.

Bit 4
update-ended interrupt enables (UIE) -- a 1 enables the update-ended interrupt and a 0 disables it. The system initializes this bit to 0.

Bit 3
square wave enabled (SQWE) -- a 1 enables the square-wave frequency as set by the rate selection bits in register A, and a 0 disables the square wave. The system initializes this bit to 0.

Bit 2
date mode (DM) -- this bit indicates whether the time and date calendar updates are to use the binary or binary coded decimal (BCD) formats. A 1 indicates binary and a 0 indicates BCD. The system initializes this bit to 0.

Bit 1
24/12 -- this bit indicates whether the hours byte is in the 24-hour or 12-hour mode. A 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. The system initializes this bit to 1.

Bit 0
Daylight Savings Enabled (DSE) -- a 1 enables daylight savings and a 0 disables daylight savings (standard time). The system initializes this bit to 0.
c Status register C

Bit 7 - Bit 4
IRQF, PF, AF, UF -- these flag bits are read-only and are affected when the AIE, PIE, and UIE bits in register B are set to 1.

Bit 3 - Bit 0
Reserved. Should be written as 0.
d Status register D

Bit 7
valid RAM Bit (VRB) -- this bit is read-only and indicates the status of the power-sense pin (battery level). A 1 indicates the battery power to the real-time clock is good. A 0 indicates the battery is dead, so RAM is not valid.

Bit 6 - Bit 0
reserved -- should be written as a 0.

 +-------------+------------------------------------------+
 |Byte address | Description                              |
 |(in hex)     |                                          |
 +-------------+------------------------------------------+
 |0            | Seconds                                  |
 +-------------+------------------------------------------+
 |1            | Second alarm                             |
 +-------------+------------------------------------------+
 |2            | Minutes                                  |
 +-------------+------------------------------------------+
 |3            | Minute alarm                             |
 +-------------+------------------------------------------+
 |4            | Hours                                    |
 +-------------+------------------------------------------+
 |5            | Hour alarm                               |
 +-------------+------------------------------------------+
 |6            | Day of week                              |
 +-------------+------------------------------------------+
 |7            | Date of month                            |
 +-------------+------------------------------------------+
 |8            | Month                                    |
 +-------------+------------------------------------------+
 |9            | Year                                     |
 +-------------+------------------------------------------+
 |a            | Status register A                        |
 |             |                                          |
 |             | Bit 7                                    |
 |             |      update in progress (UIP)  a 1       |
 |             |      indicates the time cycle update is  |
 |             |      in progress.  A 0 indicates the     |
 |             |      current date and time are available |
 |             |      to read.                            |
 |             |                                          |
 |             | Bit 6 - Bit 4                            |
 |             |      22-stage divider (DV2 through DV0)  |
 |             |      these three divider-selection bits  |
 |             |      identify which time-base frequency  |
 |             |      is being used.  The system          |
 |             |      initializes the stage divider to    |
 |             |      010, which selects a 32.768-kHz     |
 |             |      time base.                          |
 |             |                                          |
 |             | Bit 3 - Bit 0                            |
 |             |      rate selection bits (RS3 through    |
 |             |      RS0)  these bits allow the          |
 |             |      selection of a divider output       |
 |             |      frequency.  The system initializes  |
 |             |      the rate selection bits to 0110,    |
 |             |      which selects a 1.024-kHz square    |
 |             |      wave output frequency and a         |
 |             |      976.562-microsecond periodic        |
 |             |      interrupt rate.                     |
 |             |                                          |
 +-------------+------------------------------------------+
 |b            | Status register B                        |
 |             |                                          |
 |             | Bit 7                                    |
 |             |      set  a 0 updates the cycle normally |
 |             |      by advancing the counts at one per  |
 |             |      second.  A 1 aborts any update      |
 |             |      cycle in progress and the program   |
 |             |      can initialize the 14 time-bytes    |
 |             |      without any further updates         |
 |             |      occurring until a 0 is written to   |
 |             |      this bit.                           |
 |             |                                          |
 |             | Bit 6                                    |
 |             |      periodic interrupt enable (PIE)     |
 |             |      this bit is a read/write bit that   |
 |             |      allows an interrupt to occur at a   |
 |             |      rate specified by the rate and      |
 |             |      divider bits in register A.  A 1    |
 |             |      enables an interrupt and a 0        |
 |             |      disables it.  The system            |
 |             |      initializes this bit to 0.          |
 |             |                                          |
 |             | Bit 5                                    |
 |             |      alarm interrupt enable (AIE)  a 1   |
 |             |      enables the alarm interrupt and a 0 |
 |             |      disables it.  The system            |
 |             |      initializes this bit to 0.          |
 |             |                                          |
 |             | Bit 4                                    |
 |             |      update-ended interrupt enables      |
 |             |      (UIE)  a 1 enables the update-ended |
 |             |      interrupt and a 0 disables it.  The |
 |             |      system initializes this bit to 0.   |
 |             |                                          |
 |             | Bit 3                                    |
 |             |      square wave enabled (SQWE)  a 1     |
 |             |      enables the square-wave frequency   |
 |             |      as set by the rate selection bits   |
 |             |      in register A, and a 0 disables the |
 |             |      square wave.  The system            |
 |             |      initializes this bit to 0.          |
 |             |                                          |
 |             | Bit 2                                    |
 |             |      date mode (DM)  this bit indicates  |
 |             |      whether the time and date calendar  |
 |             |      updates are to use the binary or    |
 |             |      binary coded decimal (BCD) formats. |
 |             |      A 1 indicates binary and a 0        |
 |             |      indicates BCD.  The system          |
 |             |      initializes this bit to 0.          |
 |             |                                          |
 |             | Bit 1                                    |
 |             |      24/12  this bit indicates whether   |
 |             |      the hours byte is in the 24-hour or |
 |             |      12-hour mode.  A 1 indicates the    |
 |             |      24-hour mode and a 0 indicates the  |
 |             |      12-hour mode.  The system           |
 |             |      initializes this bit to 1.          |
 |             |                                          |
 |             | Bit 0                                    |
 |             |      Daylight Savings Enabled (DSE)  a 1 |
 |             |      enables daylight savings and a 0    |
 |             |      disables daylight savings (standard |
 |             |      time).  The system initializes this |
 |             |      bit to 0.                           |
 |             |                                          |
 +-------------+------------------------------------------+
 |c            | Status register C                        |
 |             |                                          |
 |             | Bit 7 - Bit 4                            |
 |             |      IRQF, PF, AF, UF  these flag bits   |
 |             |      are read-only and are affected when |
 |             |      the AIE, PIE, and UIE bits in       |
 |             |      register B are set to 1.            |
 |             |                                          |
 |             | Bit 3 - Bit 0                            |
 |             |      Reserved.  Should be written as 0.  |
 |             |                                          |
 +-------------+------------------------------------------+
 |d            | Status register D                        |
 |             |                                          |
 |             | Bit 7                                    |
 |             |      valid RAM Bit (VRB)  this bit is    |
 |             |      read-only and indicates the status  |
 |             |      of the power-sense pin (battery     |
 |             |      level).  A 1 indicates the battery  |
 |             |      power to the real-time clock is     |
 |             |      good.  A 0 indicates the battery is |
 |             |      dead, so RAM is not valid.          |
 |             |                                          |
 |             | Bit 6 - Bit 0                            |
 |             |      reserved  should be written as a 0. |
 |             |                                          |
 +-------------+------------------------------------------+

The remainder of the CMOS bytes are as follows:

CMOS configuration byte map

Byte address
(in hex)
Description
e Diagnostic status byte

Bit 7
Power status of the real-time clock chip -- a 0 indicates that the chip has not lost power, and a 1 indicates that the chip has lost power.

Bit 6
Configuration record (checksum status indicator) -- a 0 indicates that the checksum is good, and a 1 indicates that it is bad.

Bit 5
Incorrect configuration information -- this is a check, at power-on time, of the equipment of the configuration record. A 0 indicates that the configuration information is valid, and a 1 indicates it is invalid. Power-on checks require:

  • at least one diskette drive to be installed (bit 0 of byte 14 (hex) set to 1)

  • the primary display adapter setting in the configuration matches the system board's display switch setting and the actual display adapter hardware in the system

Bit 4
memory size comparison -- a 0 indicates that the power-on check determined the same memory size as in the configuration record, and a 1 indicates the memory size is different.

Bit 3
fixed disk adapter/drive C initialization status -- a 0 indicates that the adapter and drive are functioning properly and that the system can attempt to boot. A 1 indicates that the adapter and/or drive C failed initialization, which prevents the system from attempting to boot.

Bit 2
time status indicator (POST validity check) -- a 0 indicates that the time is valid, and a 1 indicates that it is invalid.

Bit 1 - Bit 0
reserved
f Shutdown status byte -- the bits in this byte are defined by the power on diagnostics.
10 Floppy disk drive type:

Bit 7 - Bit 4
type of first floppy drive installed:

0000
no drive is present

0001
double sided drive (48 TPI)

0010
high capacity drive (96 TPI)
(0011 - 1111 are reserved)

Bit 3 - Bit 0
type of second floppy drive installed
11 Reserved
12 Fixed drive type:

Bit 7 - Bit 4
first fixed drive (drive C):

0000
no drive

0001 to 1110
fixed drive type 1 - 14 as shown in the following table (also see BIOS listing at label FD_TBL.)

1111
fixed drive type 16 - 255. See description of byte 19 (hex).

Bit 3 - Bit 0
second fixed drive (drive D)
13 Reserved
14 Equipment:

Bit 7 - Bit 6
number of floppy drives installed:

00
1 drive

01
2 drives

10
reserved

11
reserved

Bit 5 - Bit 4
primary display:

00
primary display is attached to an adapter with its own BIOS, such as an EGA or VGA adapter

01
primary display is in the 40-column mode and attached to the color/graphics monitor adapter

10
primary display is in the 80-column mode and attached to the color/graphics monitor adapter

11
primary display is attached to the monochrome display and printer adapter

Bit 3 - Bit 2
not used

Bit 1
math coprocessor:

0
math coprocessor not installed

1
math coprocessor installed

Bit 0
floppy drive:

0
floppy drive not installed

1
floppy drive installed
Note that the equipment byte defines basic equipment in the system for power-on diagnostics.
15 Low-byte base memory size
valid sizes (in hex):

01 00
256KB system board RAM

02 00
512KB system board RAM

02 80
640KB - 512KB system board RAM and the IBM PC AT 128KB memory expansion option
16 High-byte base memory size
(see preceding byte description for valid sizes)
17 Low-byte expansion memory size
valid sizes (in hex):

02 00
512KB I/O adapter

04 00
1024KB I/O adapter (2 adapters)

06 00 - 3c 00
1536KB I/O adapter (3 adapters) through 15360KB I/O adapter (15MB maximum)
18 High-byte expansion memory size. (See preceding byte description for valid sizes.)
19 Type of first installed hard disk (drive C). 00000000 through 00001111 are reserved. 00010000 through 11111111 define type 16 through 255 as described in the following ``BIOS fixed disk parameters (types 16 - 22)'' table. (See BIOS listing at label FD_TBL)
1a Type of second hard disk (drive D). See preceding byte description and the ``BIOS fixed disk parameters (types 16 -22)'' table.
1b - 2d Reserved
2e High byte of checksum (calculated on addresses 10 - 2d)
2f Low byte of checksum
30 Low-byte expansion memory size. See description of byte 17 for valid sizes.
31 High-byte expansion memory size. See description of byte 17 for valid sizes.
Note that this word reflects the total expansion memory above the 1MB address space as determined at power-on time. This expansion memory size can be determined through system interrupt 15 (see BIOS listing). The base memory at power-on time is determined through the system memory-size-determine interrupt (hex 12).
32 Date century bit. BCD value for the century (BIOS interface to read and set).
33 Information flags:

Bit 7
when set, this bit indicates that the top 128KB of base memory is installed

Bit 6
this bit is set to instruct the setup utility to put out a first user message after initial setup

Bit 5 - Bit 0
reserved
34 - 3f Reserved



BIOS fixed disk parameters

Type Cylinders Heads Write Pre-comp Landing Zone
1 306 4 128 305
2 615 4 300 615
3 615 6 300 615
4 940 8 512 940
5 940 6 512 940
6 615 4 none 615
7 462 8 256 511
8 733 5 none 733
9 900 15 none 901
10 820 3 none 820
11 855 5 none 855
12 855 7 none 855
13 306 8 128 319
14 733 7 none 733
15 extended parameters (see bytes 19 and 1a)
16 612 4 all cyl 663
17 977 5 300 977
18 977 7 none 977
19 1024 7 512 1023
20 733 5 300 732
21 733 7 300 732
22 733 7 300 733
23-255 reserved

 +-------+-----------------------+-------+----------+---------+
 |Type   | Cylinders             | Heads | Write    | Landing |
 |       |                       |       | Pre-comp | Zone    |
 +-------+-----------------------+-------+----------+---------+
 |1      | 306                   | 4     | 128      | 305     |
 +-------+-----------------------+-------+----------+---------+
 |2      | 615                   | 4     | 300      | 615     |
 +-------+-----------------------+-------+----------+---------+
 |3      | 615                   | 6     | 300      | 615     |
 +-------+-----------------------+-------+----------+---------+
 |4      | 940                   | 8     | 512      | 940     |
 +-------+-----------------------+-------+----------+---------+
 |5      | 940                   | 6     | 512      | 940     |
 +-------+-----------------------+-------+----------+---------+
 |6      | 615                   | 4     | none     | 615     |
 +-------+-----------------------+-------+----------+---------+
 |7      | 462                   | 8     | 256      | 511     |
 +-------+-----------------------+-------+----------+---------+
 |8      | 733                   | 5     | none     | 733     |
 +-------+-----------------------+-------+----------+---------+
 |9      | 900                   | 15    | none     | 901     |
 +-------+-----------------------+-------+----------+---------+
 |10     | 820                   | 3     | none     | 820     |
 +-------+-----------------------+-------+----------+---------+
 |11     | 855                   | 5     | none     | 855     |
 +-------+-----------------------+-------+----------+---------+
 |12     | 855                   | 7     | none     | 855     |
 +-------+-----------------------+-------+----------+---------+
 |13     | 306                   | 8     | 128      | 319     |
 +-------+-----------------------+-------+----------+---------+
 |14     | 733                   | 7     | none     | 733     |
 +-------+-----------------------+-------+----------+---------+
 |15     | extended parameters   |       |          |         |
 |       | (see bytes 19 and 1a) |       |          |         |
 +-------+-----------------------+-------+----------+---------+
 |16     | 612                   | 4     | all cyl  | 663     |
 +-------+-----------------------+-------+----------+---------+
 |17     | 977                   | 5     | 300      | 977     |
 +-------+-----------------------+-------+----------+---------+
 |18     | 977                   | 7     | none     | 977     |
 +-------+-----------------------+-------+----------+---------+
 |19     | 1024                  | 7     | 512      | 1023    |
 +-------+-----------------------+-------+----------+---------+
 |20     | 733                   | 5     | 300      | 732     |
 +-------+-----------------------+-------+----------+---------+
 |21     | 733                   | 7     | 300      | 732     |
 +-------+-----------------------+-------+----------+---------+
 |22     | 733                   | 7     | 300      | 733     |
 +-------+-----------------------+-------+----------+---------+
 |23-255 | reserved              |       |          |         |
 +-------+-----------------------+-------+----------+---------+

Files

/etc/cmos
/dev/cmos

See also

slot(C)

Standards conformance

cmos is not part of any currently supported standard; it is an extension of AT&T System V provided by The Santa Cruz Operation, Inc.
© 2003 Caldera International, Inc. All rights reserved.
SCO OpenServer Release 5.0.7 -- 11 February 2003